FPGA Forward Error Correction Processor
The hardware of FEC processor HB14/002 is designed universally for performing of any FEC decoder (Viterbi, Turbo, LDPC Trellis). It contains FPGA Xilinx Spartan6 series and five asynchronous 4Mbit RAM memories for saving the system matrixes, data vectors, parity matrixes etc. Block diagram of the board and the example of Viterbi decoder realization are in the pictures.